In General, design of hardware with a logic circuit and the like is time-consuming. Therefore, a simulation model of hardware is fabricated in advance for simulation and evaluation of the hardware so as to develop the software in advance, avoid the specification failure, and check the performance.
Specifically, the simulation is conducted by fabricating an operation model for each function block such as a processor and a bus included in the hardware, and integrating the operation models to form a simulation model for simulating the entire operation of the hardware. Examples of the operation model include a clock model, a transaction model, a function model and the like. Each of those operation models has a different abstraction level as below.
The clock model is the operation model that describes the operation at the signal level for each clock, which corresponds to the hardware operation at the clock level. The clock model may be used mainly for verifying the operation in detail. The transaction model is the operation model that describes the operation for a single process (transaction) expressed by plural signals, and used for verifying the entire operation of the hardware. The function model is the operation model that describes the operation with respect to input data.
When the hardware performance is evaluated, it is requested to verify many functions with high precision at high speed. However, the hardware performance evaluation has a trade-off relationship between the accuracy and speed, that is, efforts to enhance the accuracy may decelerate the operation speed. In the case where all the function blocks are clock modeled to enhance the accuracy, calculation is required for every clock, thus requiring an enormous amount of time for the performance evaluation. Further, when all the function blocks are modeled, the amount of modeling becomes very large, resulting in difficulty in realizing early fabrication of the model. Therefore, models having different abstraction levels may be combined to conduct the simulation when evaluating only a part of the functions of the hardware in detail. Patent Document 1 has proposed the technology for separately evaluating the transaction model and the function model among the models, as one of the methods for conducting the aforementioned simulation.